1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to high-performance field effect transistors (FETs) fabricated on hybrid or dual substrates.
2. Description of the Related Art
To address the difference in electron and hole mobility values for NMOS and PMOS transistor devices formed on semiconductor wafers having a single crystal orientation, integrated circuit devices are increasingly fabricated with hybrid substrates with different surface orientations using semiconductor-on-insulator (SOI) wafer bonding to provide PMOS and NMOS devices with their own optimized crystal orientation. Prior attempts to integrate dual or hybrid substrates have used bulk silicon to form at least one of the PMOS and NMOS substrates, resulting in degraded performance compared to SOI substrates. For example, bulk silicon substrates have increased junction capacitance Cj and stacked gate penalty as compared to SOI substrates. The redesign and integration development costs of overcoming the performance limitations of bulk silicon can be substantial. In addition, when bulk silicon (or, for that matter, SOI silicon) is used as a single orientation surface to form FinFET CMOS devices, a forty-five degree alignment is required between NMOS and PMOS devices, creating layout and design penalties. While fully SOI dual surface orientation (DSO) integrations have been proposed to address some of these drawbacks, such integrations are overly complex, use inferior semiconductor substrate formation processes (e.g., using SIMOX techniques), use complicated substrate structures (e.g., wafer bonding), and/or do not maintain planarity between regions of different crystallographic orientation.
Accordingly, a need exists for a semiconductor manufacturing process for fabricating dual surface orientation devices which overcomes bulk performance limitations and avoids the redesign or integration costs associated with overcoming the process and performance limitations associated with bulk devices. There is also a need for an improved process for manufacturing DSO devices that obtain the performance benefits of SOI substrates, while maintaining the performance benefits of bulk substrates. A method for manufacturing aligned FinFET CMOS devices is also needed to overcome the layout and design penalties imposed by single orientation substrates. In addition, there is a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.